The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, high-k metal gates have been implemented in an effort to reduce gate leakage current, poly-silicon gate depletion, as well as other issues associated with the continued down-scaling. Transistor threshold voltage (Vt) tuning typically relies on stacking various metal layers in the high-k metal gates and then patterning the metal layers to achieve different threshold voltages. With such an approach, the number of available threshold voltages is limited by the number of metal layers that can be reliably deposited and patterned. As the scaling-down continues, such Vt tuning approach has become more difficult to implement, and typical CMOS (complementary metal-oxide semiconductor) processes can only provide four to six different threshold voltages for circuit designers. How to provide more tunable threshold voltages in today's ever-smaller devices remains a challenge.